Optimized Inexact adder for Approximate Computing Applications

Document Type : Research Paper

Authors

1 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING, SETHU INSTITUTE OF TECHNOLOGY, VIRUDHUNAGAR

2 Faculty of Engineering, Technology & Built Environment, UCSI University, Malaysia

3 IFET College of Engineering, Villupuram

4 K.Ramakrishna College of Technology

5 Kalasalingam Academy of Research and Education, Virudhunagar

Abstract

For appropriate multimedia devices, power consumption should be less and it plays a major role in designing such devices. Image compression methods make use of a variety of signal processing architectures and algorithms. In many multimedia applications, people can extract useful information from slightly inaccurate outputs. As a result, producing precise results is not essential. Adders are an essential arithmetic module in digital signal processing platforms which help to regulate the system's power and area utilisation. The detrimental development and use of approximation adders have been based on trade-off characteristics including time, area and power consumption, as well as the fault tolerance condition in some applications. This article analyses the area, latency, and power consumption of different kinds of approximate adders and existing adders. Additionally, a high-speed, power-efficient and approximate adder is developed which outperforms the current adders in terms of performance. The proposed adder can be used in arithmetic modules of several computing systems including image processing, data mining and cryptographic applications in which the exact outputs are not necessary. The proposed and existing approximate adders are synthesized by using Xilinx and the Microwind is used to measure the power consumption.

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