• Home
  • Browse
    • Current Issue
    • By Issue
    • By Author
    • By Subject
    • Author Index
    • Keyword Index
  • Journal Info
    • About Journal
    • Aims and Scope
    • Editorial Board
    • Publication Ethics
    • Peer Review Process
  • Guide for Authors
  • Submit Manuscript
  • Contact Us
 
  • Login
  • Register
Home Articles List Article Information
  • Save Records
  • |
  • Printable Version
  • |
  • Recommend
  • |
  • How to cite Export to
    RIS EndNote BibTeX APA MLA Harvard Vancouver
  • |
  • Share Share
    CiteULike Mendeley Facebook Google LinkedIn Twitter
JES. Journal of Engineering Sciences
arrow Articles in Press
arrow Current Issue
Journal Archive
Volume Volume 53 (2025)
Volume Volume 52 (2024)
Volume Volume 51 (2023)
Volume Volume 50 (2022)
Volume Volume 49 (2021)
Volume Volume 48 (2020)
Volume Volume 47 (2019)
Volume Volume 46 (2018)
Volume Volume 45 (2017)
Volume Volume 44 (2016)
Volume Volume 43 (2015)
Volume Volume 42 (2014)
Issue No 6
Issue No 5
Issue No 4
Issue No 3
Issue No 2
Issue No 1
Volume Volume 41 (2013)
Volume Volume 40 (2012)
Volume Volume 39 (2011)
Volume Volume 38 (2010)
Volume Volume 37 (2009)
Volume Volume 36 (2008)
Volume Volume 35 (2007)
Volume Volume 34 (2006)
Youness, H. (2014). DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS. JES. Journal of Engineering Sciences, 42(No 6), 1378-1391. doi: 10.21608/jesaun.2014.115115
Hassan Ali Hassan Ahmed Youness. "DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS". JES. Journal of Engineering Sciences, 42, No 6, 2014, 1378-1391. doi: 10.21608/jesaun.2014.115115
Youness, H. (2014). 'DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS', JES. Journal of Engineering Sciences, 42(No 6), pp. 1378-1391. doi: 10.21608/jesaun.2014.115115
Youness, H. DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS. JES. Journal of Engineering Sciences, 2014; 42(No 6): 1378-1391. doi: 10.21608/jesaun.2014.115115

DESIGNING AN ARCHITECTURE LEVEL MODEL FOR MULTI-CORE SYSTEMS

Article 4, Volume 42, No 6, November and December 2014, Page 1378-1391  XML PDF (1.02 MB)
Document Type: Research Paper
DOI: 10.21608/jesaun.2014.115115
View on SCiNiTO View on SCiNiTO
Author
Hassan Ali Hassan Ahmed Youness
Staff in Computers and Systems Eng. Depart, Faculty of Engineering, Minia University, Egypt
Abstract
The Architecture Level Model (ALM) as a design in space exploration in the early phases of the design process can have a dramatic impact on the area, speed, and power consumption of the resulting systems. A multi-core system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a new approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi- core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and Hardware/Software partition. The back end engine generates a System C simulation model using a well-known commercial tool model generation library to form the architecture level model. The viability and potential of the approach is demonstrated by a case study.
Keywords
ALM; Multi-core; System C; TPG; MPSoC; TLM
Main Subjects
Electrical Engineering, Computer Engineering and Electrical power and machines engineering.
Statistics
Article View: 147
PDF Download: 341
Home | Glossary | News | Aims and Scope | Sitemap
Top Top

Journal Management System. Designed by NotionWave.